Data is often transmitted in serial at a high data rate between integrated circuits. When more bandwidth is required than the desired serial data rate, data is spread across multiple serial data streams through distribution, carried across a given medium, and aggregated at the receiving end. Each serial data stream transmitted across the medium may experience a different propagation delay, causing each serial data stream to lose its associated alignment with the other serial data streams forming the link.
An integrated circuit receives a serial data signal from another integrated circuit. The receiving integrated circuit can convert the serial data in the serial data signal into parallel data to allow for operation of digital logic at lower speeds. For example, the receiving integrated circuit may convert the incoming serial data signal into successive bytes or words of parallel data. The parallel data has a lower data rate than the serial data. The parallel data is stored in the receiving integrated circuit at a lower clock frequency than the clock frequency used to sample the serial data.